The field of the invention is that of filling high aspect ratio trenches in integrated circuit processing.
As ground rule dimensions shrink in integrated circuits, the problem of filling high aspect ratio trenches increases, in particular for isolation trenches used in the shallow trench isolation process, STI, that is commonly used in advanced processing.
The industry-standard filling material and process has been silicon oxide, SiO2, deposited with the high density plasma, HDP, technique. This method has been widely adopted because it produces a high quality material that has good filling properties. Designers of integrated circuits have adapted their structural and material specifications to this process and material.
Since silicon is piezo-electric, the properties of field effect transistors, FETs, are affected by the stress on the transistor body.
In the STI process, the isolation trench material is in contact with the edges of the transistor body, so that changes in stress in that material affect the properties of the body, in particular the threshold voltage and the transistor drive.
As an additional consideration, the lengthy processes required to fabricate an integrated circuit are currently highly integrated; i.e. a change in a single process step can affect the result of steps performed before and after it, sometimes affecting steps that are not immediately before or after, but separated in time by several other steps.
It is therefore a multi-dimensional or multi-factor decision to change a process step. It is not enough that the new step produce a tougher, or thinner, or lower-density film, or take less time to put down. It is also required that the new step not produce disadvantages in other aspects of the process that outweigh the benefits.
In the particular case of isolation trench fill, the problem addressed by the present invention is that of filling high aspect ratio isolation trenches without introducing voids.
While HDP process typically shows a non-conformal deposition profile, it is known to produce voids and/or seams when filling high aspect ratio trenches, as do most of conformal deposition processes. The reason is that the material deposits on the upper surfaces of a deep trench or aperture and eventually pinches off, blocking the opening at the top and subsequently preventing material from getting down to the bottom of the trench. Present HDP techniques have a major problem in filling structures with aspect ratio greater than 4.
In order to remove blocking material from the top of isolation structures a complicated sequence of filling isolation trenches used by a major integrated circuit manufacturer involving deposition and etch cycles: First Deposit; First Wet Etch (to remove blocking material on the top); Second Deposit; Second Wet Etch; Third Deposit; and Etc (overfilling the aperture). Further processing may include a Dry etch thickness reduction followed by Chemical-Mechanical Polish (CMP)
This is obviously an expensive process and it would be highly desirable to have a process with fewer steps and lower cost that produced an equivalent filling material.
As described above, an essential consideration of the decision to introduce a new process is whether its advantages, e.g. lower cost, outweigh its disadvantages. In particular, whether the density, etch resistance, and stress of the process are close enough to the properties of HDP oxide that a major revision of the process is not required.
Another very important issue is the temperature budget of the isolation structure if at least one p-n junction or other structure having a thermal budget (meaning a limit on the time and temperature to which the element may be exposed) associated therewith has been formed on a chip before the isolation structure is built. This is also true for any dissimilar materials (for example a Si/SiGe interface to create strained silicon, etc). If any of such junction or dissimilar material interface (referred to collectively as circuit elements having a thermal budget) is built before the isolation structure then a change (increase) in isolation temperature budget leads to dopant inter-diffusion (or material inter-diffusion) and causes device degradation. In general, any change in material diffusion and dopant concentration profiles will most probably degrade device performance.
A case in point is a vertical transistor DRAM/eDRAM, where two adjacent capacitors can cross-talk to each other if the out-diffusion of As lasted long enough to travel between two buried strap contacts. Since deep trench capacitors are build before the isolation structures, the temperature budget of isolation processing should not exceed of that of the deep trench capacitor to prevent excessive As out-diffusion.
It is known that spin on materials, referred to as spin-on glass (SOG) or spin-or dielectric (SOD) have excellent filling properties.
It is also known that the other properties of these materials are much inferior to those of HDP oxide (also referred to as HDP).
For example, spin-on glass has tensile stress, a high wet etch rate and is not thermally stable.
Some work has been done with a material referred to as poly-silazane, which has good filling properties. The material has a structural formula of [SiNR1R2NR3]n, where R1, R2 and R3 are all hydrogen in the case of inorganic poly-silazane and are alkyl, aryl, or alkoxyl organic radicals in organic poly-silazane. For convenience, the term poly-silazane will be shortened to silazane.
The material has a molecular weight of between 1,000 and 10,000. It is applied as dissolved in a solvent for the spin-on step. The solvent is driven off in a pre-bake step at relatively low temperature (less than about 350 deg C.) and the material is cured by heating in various ambients.
Samsung has done work on various applications of silazane, including an interlevel dielectric film below the first level of metal (UK patent GB2361937), in which the recommended film is annealed in water vapor at a temperature of between 900 deg C. and 1000 deg C. This reference uses a two-step process of a pre-bake and high temperature steam (having water vapor) bake, without consideration of the resulting stress, or of CMP. The only planarization was that provided by the spin-on process.
Another reference by a Samsung group, “Void-Free and Low Stress Shallow Trench Isolation Technology using P-SOG for sub-0.1 um Device”, 2002, IEEE Symposium on VLSI Technology Digest of Technical Papers, pp 132, 133 (0-7803-7312-X/02) IEEE 2002, discloses a silazane process using an anneal in an oxidizing ambient at 700 deg C. (preceded by a wet etch recess) and followed by a HDP oxide cap and CMP of the HDP oxide.
Other references by a Samsung group, Pub. No. US 2002/0072246 A1, Jun. 13, 2002 and “A Highly Manufacturable, Low Thermal Budget, Void and Seam Free Pre-Metals Dielectric Process Using New SOG for beyond 60 nm DRAM and Other Devices”, 0-7803-7052-X/01, 2001 IEEE disclose a three step process for forming the interlevel dielectric below the first level of metal, in which a first bake is performed at a temperature between 350 deg C. and 500 deg C. An annealing process is performed in a broad temperature range of between 600 and 1200 deg C., preferably in an oxidizing atmosphere.
These references teach the use of a CMP process between the baking step (less than 500 deg C.) and the annealing step.
The foregoing references illustrate that semiconductor process integration is highly application specific. It is not enough that the process forms a film that insulates if the stress is not what the transistor was designed for; or if the film etches too fast and too much of it is removed in an etch step that is primarily designed to remove another portion of the structure; or if the film is damaged during a subsequent high temperature step that is critical and cannot be changed. It is also important that the isolation dielectric anneals do not shift any pre-existing p-n structures and interfaces on a chip.
The art has continued to search for an isolation trench fill process that performs the basic job of isolating satisfactorily and also has a stress and etch resistance that is close to that of industry standard HDP oxide.